Solid Oak's innovative capture tool, CoverAll™, allows architects and designers to capture and document design intent in the form of flow, state and timing diagrams early in the process during the specification phase. These diagrams are automatically converted to functional assertions, cover paths and sequences in PSL or SVA languages or using Open Verification Library(OVL) checkers to reduce generation time and eliminate the errors of manual code and assertion creation. With the optional RTLComposer™ module, designers can also automatically generate synthesizable RTL in Verilog or SystemVerilog, bind modules, module-level testbench templates in SystemVerilog or uVM, and formal verification scripts for industry standard Formal Verification tools.